In DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory), a DLL (Delay Locked Loop) circuit for generating an internal clock synchronized with an external clock is used in order to minimize operational lag within the memory. The external clock signal must be inputted at the correct duty ratio (ratio of high-level or low-level signals accommodated in one cycle; the correct duty ratio in this case is 50%) in order for the DLL circuit to operate properly. However, since a duty error of ±5% in the external clock signal is allowed by specification, and a larger duty error occurs when jitter and the like are considered, after the duty error of the internal clock is detected by a duty detection circuit, this error must be corrected using a duty correction circuit.
FIG. 8 is a simplified block diagram showing the structure of a conventional duty detection circuit.
As shown in FIG. 8, this duty detection circuit 200 comprises an integration circuit 210 for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by the DLL circuit, and generating voltage levels (DB signal and VREF signal) in accordance with the duty ratio of these internal clock signals (hereinafter referred to simply as clock signals); an amplifier 220 for amplifying the output of the integration circuit 210; and a latch circuit 230 for latching the output of the amplifier 220. The RCLK signal is an internal clock signal having the same phase as the external clock signal, and the FCLK signal is an internal clock signal having the opposite phase of the external clock signal. Therefore, the RCLK signal and the FCLK signal are complementary to each other, and the term “duty ratio” is defined by the ratio at which the RCLK signal is high-level (ratio at which the FCLK signal is low-level).
The integration circuit 210 comprises capacitors C1 and C2 connected to a signal line S1; capacitors C3 and C4 connected to a signal line S2; pre-charge transistors Tr1 through Tr3 for charging (pre-charging) the capacitors C1 and C3; activation transistors Tr4 and Tr5 for allowing the capacitors C1 and C3 to discharge (discharge); integration transistors Tr6 and Tr7 for receiving and switching the RCLK signal and the FCLK signal; and a bias transistor Tr8 inserted between the sources of the integration transistors Tr6 and Tr7 and the ground GND. A PREB (“B” stands for bar; specifically, low-active. This is the same for the ACTB signal) signal that is a pre-charge signal for initiating charging of the capacitors C1 and C3 is fed to the gates of the pre-charge transistors Tr1 through Tr3, and an ACTB signal that is an activation signal for initiating an actual integration operation is fed to the gates of the activation transistors Tr4 and Tr5.
The operation of the conventional duty detection circuit 200 will next be described with reference to FIG. 9. FIG. 9 is a waveform diagram showing the operation of the duty detection circuit 200 when the frequency of the clock signal is appropriate.
As shown in FIG. 9, when the pre-charge transistors Tr1 through Tr3 are placed in the ON state by the changing of the PREB signal to low-level, a charge is fed from the power source VCL to the capacitors C1 through C4. The capacitors C1 and C3 are thereby charged, and the capacitors C2 and C4 are discharged. When the activation transistors Tr4 and Tr5 are placed in the ON state by the changing of the ACTB signal to low-level, the charges with which the capacitors C1 and C3 were charged are alternately discharged in synchrony with the RCLK signal and FCLK signal. In other words, when the RCLK signal becomes high-level, the charge of the capacitor C1 is discharged through the activation transistor Tr4, the integration transistor Tr6, and the bias transistor Tr8; and when the FCLK signal becomes high-level the charge of the capacitor C3 is discharged through the activation transistor Tr5, the integration transistor Tr7, and the bias transistor Tr8. Since the capacitors C1 and C3 are thereby discharged during the period in which the RCLK signal and FCLK signal are each high-level, the potentials of the DB signal and the VREF signal alternately decrease in the period in which the ACTB signal is low-level, as shown in the drawing.
The final output of the integration circuit 210 is indicated by the potential difference between the VREF signal that is the potential of the signal line S1 connected to the capacitors C1 and C2 and the DB signal that is the potential of the signal line S2 connected to the capacitors C3 and C4. The difference between these potentials is amplified by the amplifier 220, whereby a DCC signal (duty correction signal) is obtained that is a 1-bit digital signal, and the DCC signal is latched in the latch circuit 230. In this arrangement, a low-level (VREF>DB) logical value for the DCC signal means that the duty ratio exceeds 50%, and a high-level (VREF<DB) logical value for the DCC signal means that the duty ratio is less than 50%. The DCC signal thus generated is fed back by the main circuit unit of the DLL circuit not shown in the drawing, and the main circuit unit of the DLL circuit changes the duty ratio of the clock signal based on this feedback. In other words, control is performed so that the duty ratio of the clock signal is reduced when the DCC signal is low-level, and so that the duty ratio of the clock signal is increased when the DCC signal is high-level. The DLL circuit causes the duty ratio of the clock signal to approach 50% by continuously performing this type of control.
The conventional duty detection circuit 200 described above has drawbacks whereby abnormal operation occurs when the frequency of the clock signal is too high or too low with respect to the pre-set reference frequency.
For example, when the frequencies of the RCLK signal and FCLK signal are near a prescribed reference frequency, as shown in FIG. 9, since the potentials of the DB signal and the VREF signal both fall within the appropriate operational range in which the amplifier 220 operates with high sensitivity, the duty error can be correctly detected.
However, as shown in FIG. 10, since the amount of discharge of the capacitors C1 and C3 is too small when the frequency of the clock signal is too high, the potential of the DB signal and VREF signal does not adequately decrease, and the level of the DB signal and VREF signal can reach or exceed the limit of the appropriate operational range of the amplifier 220. In such a state, since the potential difference between these signals is small and the difference between the two signals is easily affected by the offset of the amplifier 220 and cannot be adequately amplified, the potential for erroneous determination is high.
Conversely, as shown in FIG. 11, when the frequency of the clock signal is too low, the amount of discharge of the capacitors C1 and C3 is too large. The potential of the DB signal and VREF signal therefore significantly decreases, and the potentials of both the DB signal and the VREF signal can decrease to or become lower than the limit of the appropriate operational range of the amplifier 220 (in certain cases, discharge of the capacitors stops, and the DB signal and VREF signal both decrease to ground level (GND)). In such a state, since the difference between the two signals is also easily affected by the offset of the amplifier 220 and cannot be adequately amplified, the potential for erroneous determination is high.
Thus, in the conventional duty detection circuit 200, an adequate potential difference between the DB signal and the VREF signal is not obtained even when the frequency of the clock signal is too high or too low, and the potential for misjudgment occurring due to the effect of the offset of the amplifier 220 is extremely high. Specifically, the conventional duty detection circuit 200 has drawbacks in being extremely dependent on frequency, and in being usable only in an extremely narrow frequency bandwidth.
Therefore, an object of the present invention is to provide a duty detection circuit capable of operating normally in a wider frequency bandwidth.